Field of the Invention
The invention lies in the field of semiconductor technology. Specifically, the invention deals with minimizing the access time in semiconductor memory devices.
Semiconductor memories such as, for instance, dynamic semiconductor memories (DRAMs) are fabricated from semiconductor wafers. One wafer contains a multiplicity of identical memory chips. The dictates of production mean that the electrical parameters of these individual chips vary.
An important criterion for the power assessment and the selection of dynamic semiconductor memories among the electrical parameters is the access time. The access time is the time which elapses during a reading operation after the application of the address until the data read out are valid at the output. It is determined by the design and by a multiplicity of technological parameters (poly2 etching dimension, gateoxide, spacer TEOS, . . . )
On account of tolerances of the technological parameters and the dictates of production, the access times vary both among memory chips of an individual wafer and for memory chips of different wafers of a fabrication series. In a random selection of memory chips, the access times have a normal distribution. The proportion of memory chips whose access time lies above a specific limit can only be sold at a lower price than the faster memory chips, that is to say the memory chips which have a shorter access time.
If the technological parameters are chosen such that the proportion of fast chips increases, then the proportion of defective memory chips also increases, for example as a consequence of the punch-through effect in transistors or other production-dictated faults.
In this context, European patent application EP 0 602 355 A1 discloses a voltage generator for memories and circuits which is programmable by means of fuses. An internal voltage is increased to a desired voltage in steps using a counter and permanently set by blowing the fuses.
The relationship between the supply voltage and the access time of a semiconductor memory is disclosed in Atsumi et al., "Fast Programmable 256K Read Only Memory with On-Chip Test Circuits," in: IEEE Transactions on Electron Devices (ED 32,2/1985, No. 2, New York, USA)